Partial FPGA Rearrangement by Local

Partial rearrangement of executing tasks has been proposed as a means of alleviating the fragmentation of free logic elements that occurs on space{shared run{time reconngurable FPGA systems. In this paper, we present and assess a new solution to this strategy. Local repacking of executing tasks aims to free suucient contiguous resources for the next waiting task so as to minimize allocation and execution delays. Heuristics for the NP{hard problems of identifying and scheduling optimal task rearrangements are described and assessed by comparison with known methods.